US 12,406,959 B2
Post CMP processing for hybrid bonding
Gaius Gillman Fountain, Jr., Youngsville, NC (US); Guilian Gao, San Jose, CA (US); and Chandrasekhar Mandalapu, Morrisville, NC (US)
Assigned to ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC., San Jose, CA (US)
Filed by ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC., San Jose, CA (US)
Filed on Jul. 15, 2019, as Appl. No. 16/511,394.
Claims priority of provisional application 62/703,727, filed on Jul. 26, 2018.
Prior Publication US 2020/0035641 A1, Jan. 30, 2020
Int. Cl. H01L 23/00 (2006.01); B81C 3/00 (2006.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01); H01L 23/055 (2006.01); H01L 23/10 (2006.01); H01L 23/522 (2006.01); H01L 23/58 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/16 (2023.01); H01L 25/18 (2023.01); H01L 21/02 (2006.01); H01L 23/367 (2006.01); H01L 23/48 (2006.01); H01L 23/552 (2006.01)
CPC H01L 24/80 (2013.01) [B81C 3/001 (2013.01); H01L 21/7684 (2013.01); H01L 21/76879 (2013.01); H01L 21/78 (2013.01); H01L 23/055 (2013.01); H01L 23/10 (2013.01); H01L 23/5226 (2013.01); H01L 23/564 (2013.01); H01L 23/585 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/167 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); B81B 2203/0315 (2013.01); B81C 2203/0145 (2013.01); B81C 2203/036 (2013.01); H01L 21/02065 (2013.01); H01L 21/02076 (2013.01); H01L 21/76898 (2013.01); H01L 23/367 (2013.01); H01L 23/481 (2013.01); H01L 23/552 (2013.01); H01L 24/04 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/08121 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/80031 (2013.01); H01L 2224/80357 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06537 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06589 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1461 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microelectronic assembly, comprising:
a first substrate having a bonding surface, the bonding surface of the first substrate having a planarized topography;
a first plurality of electrically conductive features at the bonding surface of the first substrate;
a second substrate having a bonding surface, the bonding surface of the second substrate having a planarized topography and direct hybrid bonded to the bonding surface of the first substrate;
a second plurality of electrically conductive features at the bonding surface of the second substrate bonded to the first plurality of electrically conductive features while misaligned to the first plurality of electrically conductive features by a first extent, wherein the first and second plurality of electrically conductive features together define a footprint perimeter;
one or more electrically conductive contact pads disposed within an insulating layer of the second substrate and below the bonding surface of the second substrate, the one or more electrically conductive contact pads disposed inside the footprint perimeter;
one or more secondary openings in the insulating layer of the second substrate aligned to the one or more electrically conductive contact pads, the one or more secondary openings extending from the bonding surface of the second substrate to the one or more electrically conductive contact pads; and
one or more primary openings in an insulating layer of the first substrate, misaligned to the one or more secondary openings by the first extent, the one or more primary openings extending to the one or more secondary openings and providing electrical access to the one or more electrically conductive contact pads.