US 12,406,956 B2
Bilayer memory stacking with computer logic circuits shared between bottom and top memory layers
Abhishek A. Sharma, Hillsboro, OR (US); Van H. Le, Beaverton, OR (US); Kimin Jun, Portland, OR (US); Wilfred Gomes, Portland, OR (US); and Hui Jae Yoo, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Aug. 31, 2021, as Appl. No. 17/462,058.
Prior Publication US 2023/0064541 A1, Mar. 2, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 24/32 (2013.01) [H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 24/83 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/83896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device, comprising:
a first integrated circuit (IC) structure, comprising a first memory layer; and
a second IC structure, comprising a stack of a second memory layer and a compute logic layer; the second IC structure being bonded to the first IC structure,
wherein the first IC structure and the second IC structure are bonded together so that one or more components of the compute logic layer of the second IC structure are coupled to one or more components of the first memory layer.