US 12,406,955 B2
Power distribution device, power distribution system and manufacturing method thereof
Sheng-Fan Yang, Hsinchu (TW); and Yao-Tsu Chen, Hsinchu (TW)
Assigned to GLOBAL UNICHIP CORPORATION, Hisinchu (TW); and TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by GLOBAL UNICHIP CORPORATION, Hsinchu (TW); and TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Feb. 24, 2022, as Appl. No. 17/652,281.
Claims priority of application No. 111101472 (TW), filed on Jan. 13, 2022.
Prior Publication US 2023/0223370 A1, Jul. 13, 2023
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/16 (2013.01) [H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/14253 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A power distribution system, comprising:
at least one power supplier configured to provide a first reference voltage signal and a second reference voltage signal; and
a printed circuit board configured to receive the first reference voltage signal and the second reference voltage signal;
a substrate coupled to the printed circuit board and configured to output a third reference voltage signal and a fourth reference voltage signal according to the first reference voltage signal, and output a fifth reference voltage signal according to the second reference voltage signal;
a first chip coupled to the substrate and configured to receive the third reference voltage signal, the fourth reference voltage signal and the fifth reference voltage signal;
a first bump located between the substrate and the first chip, and configured to transmit the third reference voltage signal from the substrate to the first chip;
a second bump located between the substrate and the first chip, and configured to transmit the fifth reference voltage signal from the substrate to the first chip; and
a first capacitor located above the substrate and under the first chip, a first terminal of the first capacitor being coupled to the first bump, a second terminal of the first capacitor being coupled to the second bump;
a third bump located between the substrate and the first chip, and configured to transmit the fourth reference voltage signal from the substrate to the first chip;
a fourth bump located between the substrate and the first chip, and configured to transmit the fifth reference voltage signal from the substrate to the first chip;
a second capacitor located above the substrate and under the first chip, a first terminal of the second capacitor being coupled to the third bump, a second terminal of the second capacitor being coupled to the fourth bump,
wherein, the first capacitor, the second bump, the first bump, the third bump, the fourth bump and the second capacitor are arranged in order;
a first analog to digital converter; and
a first digital to analog converter,
wherein the at least one power supplier is coupled to the first analog to digital converter through a first transmission line and a second transmission line, a first terminal of the first capacitor is coupled to the first transmission line, and a second terminal of the first capacitor is coupled to the second transmission line,
wherein the at least one power supplier is coupled to the first digital to analog converter through a third transmission line and a fourth transmission line directly, a first terminal of the second capacitor is coupled to the third transmission line, and a second terminal of the second capacitor is coupled to the fourth transmission line, and
the power distribution system further comprises:
a first antenna configured to transmit a first radio frequency signal to the first analog to digital converter; and
a second antenna configured to receive a second radio frequency signal from the first digital to analog converter, wherein the first antenna is different from the second antenna.