| CPC H01L 24/05 (2013.01) [H01L 24/03 (2013.01); H01L 24/13 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02313 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/13016 (2013.01)] | 20 Claims |
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1. A chip structure, comprising:
a semiconductor substrate;
a first conductive layer over the semiconductor substrate;
a conductive via passing through the first conductive layer and electrically connected to the first conductive layer;
a conductive pad over and in direct contact with the conductive via;
a second conductive layer over and spaced apart from the first conductive layer, wherein a first lower portion of the second conductive layer is embedded in the first conductive layer, the first lower portion is a single continuous portion, and the conductive via penetrates into and through the second conductive layer and is electrically insulated from the second conductive layer;
a first dielectric layer conformally covering a second lower portion of a sidewall of the second conductive layer, wherein the first dielectric layer is in direct contact with the second lower portion of the sidewall, and the first dielectric layer is a single layer structure; and
a third conductive layer over the first dielectric layer, wherein the first dielectric layer is in direct contact with the third conductive layer, the conductive via is electrically connected to the third conductive layer, the third conductive layer has a top surface, a first upper surface, a second upper surface, a first sidewall, a second sidewall, and a third sidewall, the first upper surface is lower than the top surface and higher than the second upper surface,
wherein the top surface, the first upper surface, and the second upper surface face away from the semiconductor substrate, the first sidewall is connected between the top surface and the first upper surface, the second sidewall is connected between the first upper surface and the second upper surface, the third sidewall is connected to the second upper surface, the third conductive layer has a first corner, a second corner, and a third corner, the first corner is between the top surface and the first sidewall, the second corner is between the first upper surface and the second sidewall, the third corner is between the second upper surface and the third sidewall, and the first corner is between the second corner and the conductive via.
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