US 12,406,951 B2
Redistribution layer having a sideview zig-zag profile
Kuan-Hsiang Mao, Kaohsiung (TW); Yufu Liu, Taoyuan (TW); Tsung Nan Lo, Taoyuan (TW); and Wen Hung Huang, Kaohsiung (TW)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on May 19, 2022, as Appl. No. 17/664,117.
Prior Publication US 2023/0378107 A1, Nov. 23, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/525 (2006.01); H01L 23/528 (2006.01)
CPC H01L 24/05 (2013.01) [H01L 21/56 (2013.01); H01L 23/3171 (2013.01); H01L 23/525 (2013.01); H01L 23/5283 (2013.01); H01L 24/03 (2013.01); H01L 24/15 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/0233 (2013.01); H01L 2224/0401 (2013.01); H01L 2924/014 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device package comprising:
a semiconductor chip;
a first re-passivation layer disposed over a surface of the semiconductor device chip, wherein the first re-passivation layer includes an opening that exposes a top surface of an electrically conductive pad, and the first re-passivation layer further includes a non-planar portion relative to the surface of the semiconductor chip adjacent to the opening; and
a redistribution layer (RDL) trace disposed in conformal contact with the first re-passivation layer, wherein the RDL trace comprises a non-planar configuration relative to the surface of the semiconductor chip adjacent to the opening, wherein the non-planar configuration comprises a first area of the RDL trace having a first height and a second area of the RDL trace having a second height different than the first height.