| CPC H01L 24/05 (2013.01) [H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 2224/03845 (2013.01); H01L 2224/05087 (2013.01); H01L 2224/05096 (2013.01); H01L 2224/05098 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05186 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/08146 (2013.01); H01L 2225/06544 (2013.01)] | 18 Claims |
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1. A semiconductor device comprising:
a substrate having a first semiconductor circuit provided thereon;
first pads located on the substrate;
second pads respectively bonded to the first pads;
a first insulating layer located outside of each of the first pads on a bonding surface of the first pads and the second pads;
and
a second insulating layer located outside of each of the second pads on the bonding surface and bonded to the first insulating layer, wherein
the first pads each comprise a first area including a first conductor and a second area including a third insulating layer on the bonding surface, the second area is located inside of the first area on the bonding surface,
the first semiconductor circuit comprises one of a memory cell array and a CMOS circuit configured to control the memory cell array, and
the device further comprises a second semiconductor circuit comprising the other of the memory cell array and the CMOS circuit configured to control the memory cell array on an opposite side to the first semiconductor circuit with the bonding surface interposed between the first semiconductor circuit and the second semiconductor circuit.
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