US 12,406,946 B2
Integrated circuit for prevention of circuit design theft
Thomas Kuenemund, Munich (DE); Markus Gruetzner, Munich (DE); and Peter Egger, Baldham (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Feb. 1, 2021, as Appl. No. 17/163,597.
Claims priority of application No. 10 2020 105 474.2 (DE), filed on Mar. 2, 2020.
Prior Publication US 2021/0272916 A1, Sep. 2, 2021
Int. Cl. H01L 21/70 (2006.01); H01L 21/336 (2006.01); H01L 23/00 (2006.01); H03K 19/003 (2006.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01)
CPC H01L 23/573 (2013.01) [H03K 19/00315 (2013.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01)] 13 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
seven planar field effect transistors provided in a common substrate next to one another, wherein the seven planar field effect transistors are connected in series with one another;
wherein each field effect transistor of the seven planar field effect transistors comprises a first source/drain diffusion region, a second source/drain diffusion region, a channel region between the first source/drain diffusion region and the second source/drain diffusion region, and a gate terminal;
wherein each field effect transistor of the seven planar field effect transistors comprises at least one common source/drain diffusion region with another field effect transistor of the seven planar field effect transistors and wherein, in the at least one common source/drain diffusion region, a drain of a first transistor and a source of a second transistor, adjacent to the first transistor, share a conductor common to both the drain of the first transistor and the source of the second transistor;
wherein any common source/drain diffusion regions defined by the first source/drain diffusion region and the second source/drain diffusion region are free of vertical terminal contact material;
wherein the gate terminal of each field effect transistor of the seven planar field effect transistors comprises a vertical terminal connected thereto and composed of vertical terminal contact material for electrically contacting the respective gate terminal;
further comprising a first gate group, in which gates of at least two planar field effect transistors of the seven planar field effect transistors are connected via a first common conductor, and a second gate group, in which gates of at least two other planar field effect transistors of the seven planar field effect transistors are connected via a second common conductor, different from the first common conductor.