US 12,406,945 B2
Moisture hermetic guard ring for semiconductor on insulator devices
Mohammad Kabir, Portland, OR (US); Conor P. Puls, Portland, OR (US); Babita Dhayal, Aloha, OR (US); Han Li, Hillsboro, OR (US); Keith E. Zawadzki, Portland, OR (US); Hannes Greve, Portland, OR (US); Avyaya Jayanthinarasimham, Hillsboro, OR (US); Mukund Bapna, Hillsboro, OR (US); and Doug B. Ingerly, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 4, 2024, as Appl. No. 18/404,708.
Application 18/404,708 is a continuation of application No. 16/914,045, filed on Jun. 26, 2020, granted, now 12,014,996.
Prior Publication US 2024/0145410 A1, May 2, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 21/762 (2006.01); H01L 23/58 (2006.01); H10D 86/00 (2025.01)
CPC H01L 23/564 (2013.01) [H01L 21/76251 (2013.01); H01L 23/562 (2013.01); H01L 23/585 (2013.01); H10D 86/201 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a device layer adjacent to an interconnect layer, the device layer comprising a plurality of semiconductor devices and the interconnect layer comprising a plurality of metal interconnects;
a bond layer on a support substrate and adjacent one of the interconnect layer or the device layer; and
a structure comprising metal, wherein the structure laterally surrounds the semiconductor devices and the metal interconnects, the structure extends through the bond layer, the interconnect layer, and the device layer, and the structure is in contact with the support substrate.