US 12,406,944 B2
Moisture barrier for metal insulator metal capacitors and integrated circuit having the same
Jiro Yota, Westlake Village, CA (US); and Shiban Kishan Tiku, Camarillo, CA (US)
Assigned to Skyworks Solutions, Inc., Irvine, CA (US)
Filed by Skyworks Solutions, Inc., Irvine, CA (US)
Filed on Jun. 2, 2020, as Appl. No. 16/890,868.
Claims priority of provisional application 62/860,016, filed on Jun. 11, 2019.
Claims priority of provisional application 62/859,949, filed on Jun. 11, 2019.
Prior Publication US 2021/0020587 A1, Jan. 21, 2021
Int. Cl. H01L 23/00 (2006.01); H01L 23/06 (2006.01); H01L 23/66 (2006.01); H01Q 1/24 (2006.01); H10D 1/68 (2025.01)
CPC H01L 23/564 (2013.01) [H01L 23/06 (2013.01); H01Q 1/24 (2013.01); H10D 1/692 (2025.01); H01L 2223/6677 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor die, comprising:
a substrate layer;
a capacitor over the substrate layer, the capacitor having four sides;
a moat that surrounds the four sides of the capacitor to produce a moisture barrier between the capacitor and an area outside the moat, the moat includes a first trench portion that surrounds the capacitor and a second trench portion that partially surrounds the capacitor;
a plurality of metal layers disposed over the substrate layer that at least partially define the capacitor, the plurality of metal layers including a first metal layer that extends under the moat on all four sides of the capacitor but is smaller in size than the substrate layer, a second metal layer over a portion of the first metal layer, the second metal layer extends under the moat on at least one side of the capacitor, but not under the moat on other sides of the capacitor;
a plurality of polymer interlevel dielectric layers that partially define the capacitor, at least a first polymer interlevel dielectric layer disposed over portions of the substrate layer and under the four sides of the moat, a second polymer interlevel dielectric layer disposed over portions of the first metal layer and under the moat on at least one side of the capacitor, but not under the moat on other sides of the capacitor, the second polymer interlevel dielectric layer being tapered along the second trench portion that partially surrounds the capacitor, and a third polymer interlevel dielectric layer disposed over portions of the second metal layer, the third polymer interlevel dielectric layer being tapered along the first trench portion that surrounds the capacitor; and
a topcoat insulation layer defining a top surface of a semiconductor die, the topcoat insulation layer extends over the capacitor and the moat to inhibit moisture from traveling along the plurality of polymer interlevel dielectric layers.