| CPC H01L 23/562 (2013.01) [H01L 23/564 (2013.01); H01L 23/585 (2013.01); H01L 2924/14 (2013.01); H01L 2924/141 (2013.01); H01L 2924/1421 (2013.01); H01L 2924/143 (2013.01)] | 20 Claims |
|
1. A device comprising:
an integrated circuit located within a rectangular area defined by four sequentially connected first, second, third, and fourth linear edges, wherein the first and third linear edges are parallel, and the second and fourth linear edges are parallel;
a first seal ring surrounding the integrated circuit, wherein the first seal ring comprises a plurality of first seal portions separated from each other by a plurality of first gaps, and one of the first seal portions has a first width measured in a direction perpendicular to a lengthwise direction of the one of the first seal portions;
a second seal ring surrounding the integrated circuit and between the integrated circuit and the first seal ring, wherein the second seal ring comprises a plurality of second seal portions separated from each other by a plurality of second gaps, and a first one of the second seal portions has a second width measured in a direction perpendicular to a lengthwise direction of the first one of the second seal portions, the second width of the one of the second seal portions of the second seal ring is substantially the same as the first width of the one of the first seal portions of the first seal ring, the first one of the second seal portions has a first L-shaped top view profile comprising a first linear portion that runs along the first linear edge and a second linear portion that runs along the second linear edge, a second one of the second seal portions has a second L-shaped top view profile comprising a third linear portion that runs along the first linear edge and a fourth linear portion that runs along the fourth linear edge, and from a top view, the first and second ones of the second seal portions are free of other second seal portions therebetween,
wherein from a cross-sectional view, the first one of the second seal portions of the second seal ring further comprises a plurality of metal layers and a plurality of vias alternately arranged in a vertical direction over a substrate, and
wherein a first one of the vias, positioned within a first height layer, is the via located closest to longitudinal ends of the first and second ones of the metal layers and being sandwiched between the first and second ones of the metal layers,
wherein a second one of the vias, positioned within a second height layer, is the via located closest to the longitudinal end of the first one of the metal layers and being disposed on a bottom surface of the first one of the metal layers opposing the first one of the vias, and
wherein a footprint of the first one of the vias does not overlap with a footprint of the second one of the vias on the substrate; and
a dielectric layer surrounding the first seal ring and the second seal ring, wherein the dielectric layer comprises a plurality of first filling portions in the first gaps, respectively, and a plurality of second filling portions in the second gaps, respectively, wherein a connection line of one of the plurality of first filling portions and one of the plurality of second filling portions closest to said one of the plurality of first filling portions is not parallel to the first, second, third, and fourth linear edges of the integrated circuit.
|