US 12,406,941 B2
Dielectric slots underneath conductive vias in interconnect structure of semiconductor package and method of forming the same
Yi-Che Chiang, Hsinchu (TW); Chien-Hsun Chen, Zhutian Township (TW); Tuan-Yu Hung, Huatan Township (TW); Hsin-Yu Pan, Taipei (TW); Wei-Kang Hsieh, Tainan (TW); Tsung-Hsien Chiang, Hsinchu (TW); Chao-Hsien Huang, Kaohsiung (TW); Tzu-Sung Huang, Tainan (TW); Ming Hung Tseng, Toufen Township (TW); Wei-Chih Chen, Taipei (TW); Ban-Li Wu, Hsinchu (TW); Hao-Yi Tsai, Hsinchu (TW); Yu-Hsiang Hu, Hsinchu (TW); and Chung-Shi Liu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 24, 2022, as Appl. No. 17/752,272.
Claims priority of provisional application 63/266,523, filed on Jan. 7, 2022.
Prior Publication US 2023/0223357 A1, Jul. 13, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/10 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/105 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/214 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/3511 (2013.01); H01L 2924/35121 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a back-side redistribution structure, the back-side redistribution structure comprising:
a first dielectric layer;
a second dielectric layer on the first dielectric layer;
a first metallization pattern between the first dielectric layer and the second dielectric layer, wherein the second dielectric layer extends through the first metallization pattern to form a dielectric slot; and
a second metallization pattern, wherein the second dielectric layer is between the first metallization pattern and the second metallization pattern;
a front-side redistribution structure;
an encapsulant between the back-side redistribution structure and the front-side redistribution structure; and
a through via extending through the encapsulant, the through via being physically coupled with the second metallization pattern by a conductive via extending into the back-side redistribution structure, wherein the dielectric slot overlaps the through via in a top-down view, and wherein the conductive via is surrounded by the dielectric slot in the top-down view.