US 12,406,938 B2
Methods of forming alignment structure with trenches for semiconductor devices
Wen-Yen Chen, Hsinchu (TW); Tsai-Yu Huang, Taoyuan (TW); Huicheng Chang, Tainan (TW); and Yee-Chia Yeo, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 8, 2022, as Appl. No. 17/689,413.
Claims priority of provisional application 63/232,755, filed on Aug. 13, 2021.
Prior Publication US 2023/0050645 A1, Feb. 16, 2023
Int. Cl. H01L 23/544 (2006.01); H01L 21/02 (2006.01); H01L 21/324 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01)
CPC H01L 23/544 (2013.01) [H01L 21/0259 (2013.01); H01L 21/3247 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H01L 2223/54426 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of semiconductor device fabrication, the method comprising:
forming a plurality of trenches in a first region of a substrate;
forming a multi-layer stack over the first region and a second region of the substrate, wherein the multi-layer stack extends into the trenches, wherein the multi-layer stack comprises at least one first semiconductor layer and at least one second semiconductor layer stacked alternately; and
patterning the multi-layer stack and the substrate to form first nanostructures over first fins in the first region and second nanostructures over second fins in the second region, wherein the plurality of trenches in corresponding ones of the first fins.