US 12,406,934 B2
Semiconductor package
Juhyeon Oh, Asan-si (KR); Sunchul Kim, Hwaseong-si (KR); and Hyunki Kim, Asan-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 15, 2022, as Appl. No. 17/887,557.
Application 17/887,557 is a continuation of application No. 17/032,916, filed on Sep. 25, 2020, granted, now 11,437,326.
Application 17/032,916 is a continuation of application No. 16/424,000, filed on May 28, 2019, granted, now 10,825,774, issued on Nov. 3, 2020.
Claims priority of application No. 10-2018-0089681 (KR), filed on Aug. 1, 2018; and application No. 10-2018-0139720 (KR), filed on Nov. 14, 2018.
Prior Publication US 2022/0392846 A1, Dec. 8, 2022
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/16 (2006.01); H01L 23/31 (2006.01); H01L 21/52 (2006.01); H01L 25/18 (2023.01)
CPC H01L 23/5386 (2013.01) [H01L 23/16 (2013.01); H01L 23/3128 (2013.01); H01L 23/5385 (2013.01); H01L 23/5389 (2013.01); H01L 24/16 (2013.01); H01L 21/52 (2013.01); H01L 25/18 (2013.01); H01L 2224/16227 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a first substrate;
a second substrate provided on the first substrate;
a first semiconductor chip provided between the first substrate and the second substrate;
solder structures provided between the first substrate and the second substrate and spaced apart from the first semiconductor chip, the solder structures electrically connecting the first substrate and the second substrate; and
supporting patterns provided between the first substrate and the second substrate,
wherein the solder structures are disposed between the first semiconductor chip and the supporting patterns,
wherein, in a plan view of the semiconductor package, the supporting patterns are spaced apart from each other around sides of the first semiconductor chip, and
wherein the solder structures comprise a conductive material, and the supporting patterns comprise an insulating material.