US 12,406,932 B2
Memory circuitry and method used in forming memory circuitry
Yiping Wang, Boise, ID (US); Jiewei Chen, Meridian, ID (US); and Collin Howder, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 4, 2022, as Appl. No. 17/881,308.
Prior Publication US 2024/0047362 A1, Feb. 8, 2024
Int. Cl. H01L 23/535 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H01L 23/535 (2013.01) [H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 34 Claims
OG exemplary drawing
 
1. A method used in forming memory circuitry, comprising:
forming a stack comprising vertically-alternating first tiers and second tiers, the stack extending from a memory-array region into a stair-step region, the stair-step region comprising a cavity comprising a flight of stairs, the first tiers being conductive and the second tiers being insulative at least in a finished-circuitry construction;
forming a lining in and that less-than-fills the cavity atop treads of the stairs, individual of the treads comprising conducting material of one of the first tiers in the finished-circuitry construction;
replacing the lining that is atop the treads with at least one of metal material, polysilicon, or SiGe and providing insulative material in remaining volume of the cavity directly above the at least one of the metal material, the polysilicon, or the SiGe; and
forming conductive vias through the insulative material and the at least one of the metal material, the polysilicon, or the SiGe; individual of the conductive vias being directly above and directly against the conducting material of one of the individual treads.