US 12,406,931 B2
Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication
Atul Madhavan, Portland, OR (US); Nicholas J. Kybert, Portland, OR (US); Mohit K. Haran, Hillsboro, OR (US); and Hiten Kothari, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 15, 2022, as Appl. No. 17/841,479.
Application 17/841,479 is a division of application No. 16/147,541, filed on Sep. 28, 2018, granted, now 11,393,754.
Prior Publication US 2022/0310516 A1, Sep. 29, 2022
Int. Cl. H01L 23/535 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/45 (2006.01); H01L 29/51 (2006.01)
CPC H01L 23/535 (2013.01) [H01L 21/02126 (2013.01); H01L 21/02167 (2013.01); H01L 21/0217 (2013.01); H01L 21/02178 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 27/0886 (2013.01); H01L 29/518 (2013.01); H01L 21/02164 (2013.01); H01L 21/0228 (2013.01); H01L 21/0276 (2013.01); H01L 21/31144 (2013.01); H01L 29/45 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon;
a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon;
a first dielectric etch stop layer directly on and continuous over the trench insulating layers and the gate insulating layers;
a second dielectric etch stop layer directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer;
an interlayer dielectric material on the second dielectric etch stop layer;
an opening in the interlayer dielectric material, in the second dielectric etch stop layer, in the first dielectric etch stop layer, and in one of the gate insulating layers; and
a conductive structure in the opening, the conductive structure in direct contact with a corresponding one of the gate structures.