	US 12,406,929 B2
	Semiconductor memory device
Inho Roh, Seoul (KR); Donghwa Kwak, Suwon-si (KR); Kyung Don Mun, Asan-si (KR); and Wonsok Lee, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 26, 2022, as Appl. No. 17/896,241.
Claims priority of application No. 10-2021-0176536 (KR), filed on Dec. 10, 2021.
Prior Publication US 2023/0187352 A1, Jun. 15, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 23/522 (2006.01); H10B 12/00 (2023.01)

CPC H01L 23/5283 (2013.01) [H01L 23/5226 (2013.01); H10B 12/0335 (2023.02); H10B 12/053 (2023.02); H10B 12/315 (2023.02); H10B 12/34 (2023.02); H10B 12/482 (2023.02); H10B 12/488 (2023.02)]

20 Claims

1. A semiconductor memory device, comprising:

a substrate including active regions, the active regions having first impurity regions and second impurity regions;

word lines on a first surface of the substrate, the word lines extending in a first direction;

first bit lines on the word lines, the first bit lines extending in a second direction crossing the first direction, and the first bit lines being connected to the first impurity regions;

first contact plugs between the first bit lines, the first contact plugs being connected to the second impurity regions, respectively;

second bit lines on a second surface of the substrate, the second bit lines being electrically connected to the first impurity regions; and

a first capacitor on the first contact plugs.