US 12,406,928 B2
Three-dimensional memory devices and fabricating methods thereof
Yuancheng Yang, Hubei (CN); Dongxue Zhao, Hubei (CN); Tao Yang, Hubei (CN); Lei Liu, Hubei (CN); Di Wang, Hubei (CN); Kun Zhang, Hubei (CN); Wenxi Zhou, Hubei (CN); Zhiliang Xia, Hubei (CN); and Zongliang Huo, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on May 6, 2022, as Appl. No. 17/738,715.
Prior Publication US 2023/0361030 A1, Nov. 9, 2023
Int. Cl. H01L 23/528 (2006.01); H10B 41/20 (2023.01); H10B 43/20 (2023.01)
CPC H01L 23/5283 (2013.01) [H10B 41/20 (2023.02); H10B 43/20 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A method for forming a memory structure, comprising:
forming a bottom conductive layer on a substrate;
forming a bottom isolation layer on the bottom conductive layer;
forming a memory stack on the bottom isolation layer, the memory stack comprising a plurality of dielectric layers alternately arranged with a plurality of conductive layers;
forming an opening penetrating the memory stack and bottom isolation layer to expose the bottom conductive layer;
forming a cap layer on the bottom conductive layer and filling a first portion of the opening;
forming a cylindrical body on the cap layer and filing a second portion of the opening;
forming a top contact on the cylindrical body and filling a third portion of the opening; and
forming a plurality of interconnection structures to electrically couple the bottom conductive layer, the plurality of conductive layers of the memory stack, and the top contact.