US 12,406,925 B2
Bare-die smart bridge connected with copper pillars for system-in-package apparatus
Georg Seidemann, Landshut (DE); Thomas Wagner, Regelsbach (DE); Andreas Wolter, Regensburg (DE); and Bernd Waidhas, Pettendorf (DE)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 17, 2021, as Appl. No. 17/555,219.
Application 17/555,219 is a continuation of application No. 16/349,170, granted, now 11,270,941, previously published as PCT/US2016/069176, filed on Dec. 29, 2016.
Prior Publication US 2022/0115323 A1, Apr. 14, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/528 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/532 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 25/16 (2023.01)
CPC H01L 23/5283 (2013.01) [H01L 21/561 (2013.01); H01L 21/76885 (2013.01); H01L 23/00 (2013.01); H01L 23/481 (2013.01); H01L 23/53228 (2013.01); H01L 23/5385 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/16 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 24/96 (2013.01); H01L 2224/02371 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A system-in-package apparatus, comprising:
a semiconductive bridge in a molding compound, the semiconductive bridge having a top surface, a bottommost surface, a first side between the top surface and the bottommost surface, and a second side between the top surface and the bottommost surface, wherein the bottommost surface of the semiconductive bridge is at a same level as a bottommost surface of the molding compound;
a first plurality of interconnects laterally adjacent to the first side of the semiconductive bridge;
a second plurality of interconnects laterally adjacent to the second side of the semiconductive bridge;
a first IC device electrically coupled to the top surface of the semiconductive bridge, and the first IC device electrically coupled to the first plurality of interconnects;
a second IC device electrically coupled to the top surface of the semiconductive bridge, and the second IC device electrically coupled to the second plurality of interconnects;
a capping material between and in contact with the first IC device and the second IC device, the capping material between the first IC device and the top surface of the semiconductive bridge, and the capping material between the second IC device and the top surface of the semiconductive bridge;
a first plurality of bumps beneath the bottommost surface of the semiconductive bridge, the first plurality of bumps within the first side and the second side of the semiconductive bridge;
a second plurality of bumps beneath the first plurality of interconnects; and
a third plurality of bumps beneath the second plurality of interconnects.