US 12,406,924 B2
Interconnection structure and methods of forming the same
Wei-Hao Liao, Taichung (TW); Hsi-Wen Tien, Hsinchu (TW); Yu-Teng Dai, New Taipei (TW); Chih Wei Lu, Hsinchu (TW); Hsin-Chieh Yao, Hsinchu (TW); and Chung-Ju Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 20, 2023, as Appl. No. 18/224,209.
Application 18/224,209 is a division of application No. 17/313,217, filed on May 6, 2021, granted, now 11,756,884.
Prior Publication US 2023/0361029 A1, Nov. 9, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/528 (2013.01) [H01L 21/76802 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 21/76895 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An interconnection structure, comprising:
a dielectric layer;
a first conductive feature disposed in the dielectric layer;
a second conductive feature disposed over the first conductive feature, the second conductive feature comprising a first conductive layer disposed on and in contact with the first conductive feature, a second conductive layer disposed on and in contact with the first conductive layer, and a third conductive layer disposed on and in contact with the second conductive layer, wherein the first conductive layer, the second conductive layer and the third conductive layer have substantially the same width, and a thickness of the third conductive layer is about 5% to 15% of a total thickness of the second conductive feature;
a third conductive feature disposed over the dielectric layer, the third conductive feature comprising a fourth conductive layer disposed over the dielectric layer, a fifth conductive layer disposed on the fourth conductive layer, and a sixth conductive layer disposed on the fifth conductive layer, wherein the fourth conductive layer, the fifth conductive layer and the sixth conductive layer have substantially the same width;
a dielectric fill disposed over the dielectric layer between the second conductive feature and the third conductive feature; and
a continuous etch stop layer disposed on and in contact with the third conductive layer of the second conductive feature, the third conductive feature, and the dielectric fill.