US 12,406,923 B2
One-time-programmable memory device including an antifuse structure and methods of forming the same
Meng-Sheng Chang, Chu-bei (TW); Chia-En Huang, Xinfeng Township (TW); and Yih Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jun. 30, 2022, as Appl. No. 17/854,008.
Application 17/854,008 is a division of application No. 16/901,038, filed on Jun. 15, 2020, granted, now 11,605,639.
Prior Publication US 2022/0328507 A1, Oct. 13, 2022
Int. Cl. H01L 23/525 (2006.01); H01L 21/28 (2025.01); H10B 20/25 (2023.01)
CPC H01L 23/5252 (2013.01) [H01L 21/28008 (2013.01); H10B 20/25 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A one time programmable (OTP) memory device comprising:
a field effect transistor including a source region, a drain region, a gate dielectric, and a gate electrode and located on a substrate;
a semiconductor-insulator-metal (SIM) antifuse structure including the drain region that constitutes a first node, a drain-side metallic material portion that constitutes a second node that is spaced from the first node, and an antifuse dielectric layer located between the first node and the second node, wherein a periphery of a top surface of the antifuse dielectric layer is laterally offset relative to a periphery of a bottom surface of the drain-side metallic material portion; and
an etch stop dielectric layer contacting a top surface of the drain region and having an opening therein, wherein:
the opening has a lesser area than an area of the top surface of the drain region;
the antifuse dielectric layer comprises a portion that is located within the opening;
a bottom surface of the antifuse dielectric layer is located within a first horizontal plane including a bottom surface of the etch stop dielectric layer; and
a top surface of the antifuse dielectric layer is located within a second horizontal plane including a top surface of the etch stop dielectric layer.