US 12,406,922 B2
Semiconductor structure and manufacturing method thereof
Chin-Cheng Yang, Kaohsiung (TW)
Assigned to MACRONIX International Co., Ltd., Hsinchu (TW)
Filed by MACRONIX International Co., Ltd., Hsinchu (TW)
Filed on Aug. 31, 2022, as Appl. No. 17/900,587.
Prior Publication US 2024/0071906 A1, Feb. 29, 2024
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/768 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate; and
a pad structure located on the substrate and comprising:
material pairs stacked on the substrate to form a stair step structure, wherein each of the material pairs comprises a conductive layer and a dielectric layer located on the conductive layer; and
pads, wherein each of the pads comprises:
a conductive pillar embedded in the material pair and connected to the conductive layer of the material pair; and
a pad layer located on the conductive pillar, wherein
a thickness of the pad is greater than a thickness of the conductive layer.