US 12,406,919 B2
Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells
Sanh D. Tang, Boise, ID (US); Roger W. Lindsay, Boise, ID (US); and Krishna K. Parat, Palo Alto, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 14, 2024, as Appl. No. 18/441,767.
Application 17/837,923 is a division of application No. 16/850,692, filed on Apr. 16, 2020, granted, now 11,393,748.
Application 15/095,208 is a division of application No. 14/602,559, filed on Jan. 22, 2015, granted, now 9,318,430, issued on Apr. 19, 2016.
Application 14/602,559 is a division of application No. 13/085,083, filed on Apr. 12, 2011, granted, now 8,945,996, issued on Feb. 3, 2015.
Application 18/441,767 is a continuation of application No. 17/837,923, filed on Jun. 10, 2022, granted, now 11,923,289.
Application 16/850,692 is a continuation of application No. 16/654,908, filed on Oct. 16, 2019, granted, now 10,658,285, issued on May 19, 2020.
Application 16/654,908 is a continuation of application No. 15/900,188, filed on Feb. 20, 2018, granted, now 10,475,737, issued on Nov. 12, 2019.
Application 15/900,188 is a continuation of application No. 15/397,919, filed on Jan. 4, 2017, granted, now 9,929,175, issued on Mar. 27, 2018.
Application 15/397,919 is a continuation of application No. 15/095,208, filed on Apr. 11, 2016, granted, now 9,564,471, issued on Feb. 7, 2017.
Prior Publication US 2024/0186234 A1, Jun. 6, 2024
Int. Cl. H01L 23/52 (2006.01); G11C 13/00 (2006.01); H01L 23/528 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H01L 23/52 (2013.01) [G11C 13/0007 (2013.01); H01L 23/528 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 63/00 (2023.02); H10B 63/845 (2023.02); H10N 70/8822 (2023.02); H10N 70/8825 (2023.02); H10N 70/8828 (2023.02); H10N 70/8833 (2023.02); H10N 70/8836 (2023.02); G11C 2213/11 (2013.01); G11C 2213/31 (2013.01); G11C 2213/32 (2013.01); G11C 2213/71 (2013.01); G11C 2213/75 (2013.01); H01L 2924/0002 (2013.01); H10B 41/35 (2023.02); H10N 70/882 (2023.02); H10N 70/883 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor construction comprising:
a substrate comprising a semiconductive material;
a stack of horizontally extending features over an upper surface of the substrate, the stack comprising a primary portion and a stair step portion, at least some of the features extending farther horizontally in the stair step portion;
operative structures extending vertically through the features in the primary portion, the operative structures comprising interconnected channels of a plurality of vertically oriented transistors; and
dummy structures extending vertically through the features in the stair step portion and into the semiconductive material of the substrate, the dummy structures arranged in the stair step portion with a first number-density being different from a second number-density of an arrangement of the operative structures in the primary portion.