US 12,406,916 B2
Via plug capacitor
Santosh Gangal, Bangalore (IN); and Tin Poay Chuah, Bayan Baru (MY)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 17, 2021, as Appl. No. 17/204,592.
Prior Publication US 2022/0302007 A1, Sep. 22, 2022
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H05K 1/11 (2006.01); H05K 1/16 (2006.01); H10D 1/47 (2025.01); H10D 1/68 (2025.01)
CPC H01L 23/49827 (2013.01) [H01L 21/486 (2013.01); H01L 24/16 (2013.01); H05K 1/113 (2013.01); H05K 1/162 (2013.01); H05K 1/167 (2013.01); H10D 1/474 (2025.01); H10D 1/696 (2025.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2924/15311 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an electronic substrate comprising a via extending at least partially between a first side and an opposing second side of the electronic substrate;
a capacitive element within the via;
a first electrode and a second electrode coupled to the capacitive element, the capacitive element comprising:
a first conductor in contact with the first electrode;
a second conductor in contact with the second electrode; and
a dielectric material between the first conductor and the second conductor, wherein the first or the second conductor comprises a metal comprising one of silver, palladium, or tantalum and the dielectric material comprises an oxide of the metal; and
an adhesive between and directly on the capacitive element and a surface of the via, wherein the adhesive is directly on the dielectric material of the capacitive element, and wherein the first electrode comprises a pad over the first side of the electronic substrate, the pad in contact with the adhesive.