US 12,406,915 B2
Plated metal layer in power packages
Jonathan Almeria Noquil, Plano, TX (US); Makarand Ramkrishna Kulkarni, Dallas, TX (US); Osvaldo Jorge Lopez, Annandale, TX (US); Yiqi Tang, Allen, TX (US); Rajen Manicon Murugan, Dallas, TX (US); and Liang Wan, Chengdu (CN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Oct. 10, 2023, as Appl. No. 18/484,310.
Application 18/484,310 is a continuation of application No. 17/334,491, filed on May 28, 2021, granted, now 11,784,114.
Claims priority of provisional application 63/122,903, filed on Dec. 8, 2020.
Prior Publication US 2024/0047330 A1, Feb. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/49822 (2013.01) [H01L 23/49844 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16238 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A semiconductor package including a power transistor, comprising:
a semiconductor die including a gate pad, the semiconductor die attached to a package substrate, the package substrate including:
a dielectric;
a metal layer in the dielectric;
a plated metal layer plated on top of the metal layer and having a thickness ranging from 30 microns to 60 microns.