US 12,406,912 B2
Semiconductor package
Hyung Gyun Noh, Hwaseong-si (KR); Keun-Ho Rhew, Seoul (KR); Sang Woo Pae, Suwon-si (KR); Jin Soo Bae, Seongnam-si (KR); Deok-Seon Choi, Hwaseong-si (KR); and Il-Joo Choi, Anyang-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 2, 2022, as Appl. No. 17/591,144.
Claims priority of application No. 10-2021-0095686 (KR), filed on Jul. 21, 2021.
Prior Publication US 2023/0029151 A1, Jan. 26, 2023
Int. Cl. H01L 23/498 (2006.01); H01L 23/14 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/49811 (2013.01) [H01L 23/14 (2013.01); H01L 23/53228 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a first device and a second device that are electrically connected to each other,
wherein the first device includes a substrate, a first pad formed on an upper side of the substrate, and a passivation film formed on the upper side of the substrate and formed to surround the first pad,
the second device includes a second pad placed to face the first pad, and
the first pad has a center pad having a first elastic modulus and an edge pad having a second elastic modulus smaller than the first elastic modulus, the edge pad formed to surround the center pad and to directly contact the passivation film,
wherein an upper side of the center pad, an upper side of the edge pad, and an upper side of the passivation film are located on the same plane,
wherein a lower side of the center pad, a lower side of the edge pad, and a lower side of the passivation film are located on the same plane, and
wherein the first pad and the second pad are electrically connected to each other through a solder bump.