CPC H01L 23/4821 (2013.01) [H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01)] | 20 Claims |
1. A method for manufacturing a semiconductor structure, comprising:
forming a gate structure over a substrate;
forming a first dielectric layer over the gate structure;
forming a source/drain (S/D) structure adjacent to the gate structure;
forming an S/D contact structure over the S/D structure;
forming a second dielectric layer over the S/D contact structure;
forming a first trench through the first dielectric layer and the second dielectric layer over the gate structure to expose a top surface of the gate structure;
forming a gate contact structure in the first trench, wherein the gate contact structure is in direct contact with the gate structure;
removing a top portion of the gate contact structure; and
forming a bridging contact structure over the gate contact structure and the S/D contact structure, wherein the bridging contact structure is in direct contact with the gate contact structure and the S/D contact structure.
|