US 12,406,906 B2
Through mold interconnect drill feature
Robert M. Nickerson, Chandler, AZ (US); Rees Winters, Glendale, AZ (US); and Purushotham Kaushik Muthur Srinath, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 16, 2023, as Appl. No. 18/318,523.
Application 18/318,523 is a continuation of application No. 16/550,773, filed on Aug. 26, 2019, granted, now 11,705,383.
Prior Publication US 2023/0290708 A1, Sep. 14, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 23/315 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An electronic package, comprising:
a first die coupled to a package substrate, the first die having a top surface;
a second die coupled to a first portion of the top surface of the first die, the second die having a top surface;
a first mold layer over a second portion of the top surface of the first die, the first mold layer laterally adjacent to and in direct contact with an entirety of a sidewall of the second die, and the first mold layer having a top surface co-planar with the top surface of the second die;
a second mold layer on the package substrate, the second mold layer laterally adjacent to and in contact with the first mold layer, and the second mold layer having a top surface co-planar with the top surface of the first mold layer;
a through mold opening in the second mold layer, the through mold opening having a center and a top; and
a through mold interconnect in the through mold opening, the through mold interconnect having a portion above the top of the through mold opening, the portion of the through mold interconnect having a center offset from the center of the through mold opening, wherein the through mold interconnect is laterally spaced apart from both the first die and the second die.