| CPC H01L 23/481 (2013.01) [H01L 23/5226 (2013.01)] | 20 Claims |
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1. A semiconductor device comprising:
a semiconductor substrate having a first surface and a second surface, opposing each other, and having power arrangement regions;
a circuit element disposed on the semiconductor substrate;
a first interconnection structure disposed on the first surface of the semiconductor substrate and including first interconnection patterns and power lines;
a second interconnection structure disposed on the second surface of the semiconductor substrate and including second interconnection patterns;
insulating structures disposed in the power arrangement regions; and
through-electrodes passing through each of the power arrangement regions and contacting the power lines,
wherein the first interconnection patterns include first interconnection lines disposed on different levels from each other,
wherein the power lines are disposed on a same height level as a first interconnection line, among the first interconnection lines, and are parallel to each other, wherein the power lines extend in a first horizontal direction,
wherein the power arrangement regions are parallel to each other and extend in a second horizontal direction, substantially perpendicular to the first horizontal direction, and
wherein, in a plan view, intersection regions, in which the power arrangement regions and the power lines intersect, include active intersection regions and dummy intersection regions,
wherein the active intersection regions and the dummy intersection regions include a plurality of first active intersection regions, one dummy intersection region, and a plurality of second active intersection regions, sequentially arranged in the second horizontal direction, and
wherein, in a plan view, the through-electrodes are disposed in the active intersection regions and are not disposed in the dummy intersection regions.
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