US 12,406,892 B2
Display defect monitoring structure
Chu Fu Chen, Hsinchu (TW); and Chun Hao Liao, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 17, 2023, as Appl. No. 18/171,286.
Claims priority of provisional application 63/375,536, filed on Sep. 13, 2022.
Prior Publication US 2024/0087966 A1, Mar. 14, 2024
Int. Cl. H10K 59/131 (2023.01); H01L 21/66 (2006.01); H10B 10/00 (2023.01); H10K 59/12 (2023.01); H10K 59/127 (2023.01)
CPC H01L 22/30 (2013.01) [H01L 22/12 (2013.01); H01L 22/14 (2013.01); H10B 10/12 (2023.02); H10K 59/1201 (2023.02); H10K 59/127 (2023.02); H10K 59/131 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A driver structure for an organic light-emitting diode (OLED) device, the driver structure having a plurality of pixel regions arranged in rows and columns, wherein the driver structure comprises:
a front-end-of-line (FEOL) layer comprising a plurality of control transistors;
a back-end-of-line (BEOL) layer disposed on the FEOL layer, wherein the BEOL layer comprises:
a multilayer interconnect (MLI) structure; and
a customer BEOL electrical checking structure having a plurality of memory cells that include a first memory cell, wherein the first memory cell is vertically aligned with and corresponds to two adjacent pixel regions comprising a first pixel region and a second pixel region; and
a customer BEOL layer disposed on the BEOL layer, the customer BEOL layer comprising a plurality of OLED bottom structures, the plurality of OLED bottom structures comprising:
a first OLED bottom structure, a second OLED bottom structure, and a third OLED bottom structure corresponding to the first pixel region and connected in series to form a first electrical path that is electrically connected to the first memory cell; and
a fourth OLED bottom structure, a fifth OLED bottom structure, and a sixth OLED bottom structure corresponding to the second pixel region and connected in series to form a second electrical path that is electrically connected to the first memory cell;
wherein each of the OLED bottom structures corresponds to and is electrically connected to one of the plurality of control transistors through the MLI structure; and
wherein the first memory cell is configured to detect an anomaly of the first electrical path and the second electrical path.