| CPC H01L 21/76816 (2013.01) [H01L 21/0332 (2013.01); H01L 21/76895 (2013.01); H01L 23/5283 (2013.01); H10D 84/0149 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H01L 23/485 (2013.01); H01L 23/53233 (2013.01); H01L 23/53238 (2013.01); H01L 2924/0002 (2013.01)] | 20 Claims |

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1. A device comprising:
a first dielectric layer disposed over a substrate;
a first conductive feature disposed within the first dielectric layer;
a second conductive feature disposed within the first dielectric layer;
a third conductive feature over the substrate, wherein the first conductive feature is over and electrically coupled to the third conductive feature;
a fourth conductive feature in the substrate, wherein the second conductive feature extends continuously and physically contacts the fourth conductive feature, wherein the third conductive feature and the fourth conductive feature comprise a gate electrode and a doped region, respectively, and wherein the third conductive feature and the fourth conductive feature are arranged along a first direction; and
a conductive line connected to the first conductive feature and the second conductive feature, the conductive line including:
a line-like portion having a first length along the first direction and a first width along a second direction, wherein the line-like portion is aligned to the first conductive feature and the second conductive feature, and wherein the line-like portion is directly above, vertically overlaps, and physically contacts the second conductive feature, and
a first line-end portion connected to the line-like portion and disposed over the first conductive feature, wherein the first line-end portion has a second width along the second direction that is larger than the first width, wherein the first line-end portion has a second length along the first direction that is smaller than the first length.
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