US 12,406,876 B2
Semiconductor structure including isolation structure with dielectric stack and method of forming the same
Kui-Yu Chen, Miaoli (TW); Chi-Ruei Yeh, New Taipei (TW); and Tsung-Yu Chiang, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jan. 28, 2022, as Appl. No. 17/587,299.
Prior Publication US 2023/0245921 A1, Aug. 3, 2023
Int. Cl. H01L 21/762 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H01L 21/76224 (2013.01) [H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H10D 84/0149 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a fin structure on the substrate;
forming a first dummy gate on the fin structure;
forming a trench to penetrate the first dummy gate and the fin structure;
forming a dielectric stack in the trench;
removing a top portion of the dielectric stack in the trench to leave a lower portion of the dielectric stack in the trench; and
forming a protective layer in the trench and directly on the lower portion of the dielectric stack, wherein the forming of the protective layer includes:
depositing a cap layer over the dielectric stack;
patterning the cap layer and the dielectric stack to form an opening aligned with the trench; and
filling the opening with the protective layer.