US 12,406,859 B2
Gate structures in semiconductor devices
Hsiang-Pi Chang, New Taipei (TW); Chung-Liang Cheng, Changhua County (TW); I-Ming Chang, Shinchu (TW); Yao-Sheng Huang, Kaohsiung (TW); and Huang-Lin Chao, Hillsboro, OR (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 13, 2023, as Appl. No. 18/168,392.
Application 18/168,392 is a continuation of application No. 17/406,879, filed on Aug. 19, 2021, granted, now 11,581,416.
Prior Publication US 2023/0187526 A1, Jun. 15, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/3115 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H01L 21/3115 (2013.01) [H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 64/017 (2025.01); H10D 64/681 (2025.01); H10D 64/691 (2025.01); H10D 84/0144 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a fin structure disposed on the substrate;
a first metal oxide layer disposed on the fin structure;
a second metal oxide layer disposed on the first metal oxide layer, wherein the second metal oxide layer is different from the first metal oxide layer;
a first dielectric layer disposed on the second metal oxide layer, wherein metals of the first and second metal oxide layers have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer; and
a gate metal fill layer on the first dielectric layer.