US 12,406,857 B2
Method for fabricating array structure of columnar capacitor and semiconductor structure
Qiang Wan, Hefei (CN); Kangshu Zhan, Hefei (CN); and Jun Xia, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 9, 2023, as Appl. No. 18/151,469.
Application 18/151,469 is a continuation of application No. PCT/CN2022/072659, filed on Jan. 19, 2022.
Claims priority of application No. 202110973338.5 (CN), filed on Aug. 24, 2021.
Prior Publication US 2023/0298899 A1, Sep. 21, 2023
Int. Cl. H01L 21/311 (2006.01); H10D 1/68 (2025.01)
CPC H01L 21/31144 (2013.01) [H10D 1/68 (2025.01)] 13 Claims
OG exemplary drawing
 
1. A method for fabricating an array structure of a columnar capacitor, comprising:
providing a substrate provided with a plurality of conductive pads therein, wherein a first sacrificial layer, an intermediate support layer, a second sacrificial layer, a top support layer and a mask layer are stacked on the substrate, the substrate being divided into an array region and a peripheral region, a thickness of the mask layer positioned in the array region being less than a thickness of the mask layer positioned in the peripheral region, and a plurality of capacitor holes in the array region penetrating through the mask layer, the top support layer, the second sacrificial layer, the intermediate support layer and the first sacrificial layer, to expose the plurality of conductive pads;
forming a photoresist layer, wherein the photoresist layer is filled in the plurality of capacitor holes and covers the mask layer in the array region;
removing a part of the mask layer in the peripheral region, wherein an upper surface of a remaining part of the mask layer in the peripheral region is flush with an upper surface of the mask layer in the array region;
removing the photoresist layer on a surface of the mask layer and etching the mask layer by using the top support layer as an etching stop layer;
forming a third sacrificial layer, wherein the third sacrificial layer covers the top support layer;
removing the photoresist layer;
filling a conductive material in the plurality of capacitor holes to form a lower electrode, wherein the lower electrode is electrically connected to the plurality of conductive pads;
forming an auxiliary layer, wherein the auxiliary layer covers the third sacrificial layer and the lower electrode;
patterning the auxiliary layer, the third sacrificial layer and the top support layer, and removing the third sacrificial layer and the second sacrificial layer;
patterning the intermediate support layer and removing the first sacrificial layer and the auxiliary layer;
forming a dielectric layer, wherein the dielectric layer covers an exposed surface of the substrate, an exposed surface of the lower electrode, an exposed surface of the intermediate support layer, and an exposed surface of the top support layer; and
forming an upper electrode, wherein the upper electrode covers a surface of the dielectric layer.