US 12,406,848 B2
Method of fabricating a gate cut feature for multi-gate semiconductor devices
Ming-Yuan Wu, Hsinchu (TW); Da-Wen Lin, Hsinchu (TW); Yi-Ting Fu, Hsinchu (TW); Hsu-Chieh Cheng, Hsinchu (TW); and Min Jiao, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on May 4, 2022, as Appl. No. 17/736,898.
Claims priority of provisional application 63/222,538, filed on Jul. 16, 2021.
Prior Publication US 2023/0015372 A1, Jan. 19, 2023
Int. Cl. H01L 21/28 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01)
CPC H01L 21/28123 (2013.01) [H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 84/0128 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a fin protruding from a substrate;
forming a first dielectric feature adjacent to the fin over the substrate;
forming a cladding layer over the fin and the first dielectric feature;
removing a portion of the cladding layer to form an opening, wherein the opening exposes the first dielectric feature; and
forming a second dielectric feature adjacent to the cladding layer, wherein the second dielectric feature fills the opening;
forming a dummy gate stack over the fin and the second dielectric feature;
forming source/drain (S/D) features in S/D regions of the fin not covered by the dummy gate stack;
removing the dummy gate stack to form a gate trench, the gate trench exposing the cladding layer;
removing the cladding layer; and
forming a metal gate stack in the gate trench, wherein the second dielectric feature divides the metal gate stack.