US 12,406,747 B2
Memory location mapping and unmapping
Shivananda Shetty, Fremont, CA (US); and Stefano Amato, San Jose, CA (US)
Assigned to Infineon Technologies LLC, San Jose, CA (US)
Filed by Infineon Technologies LLC, San Jose, CA (US)
Filed on Oct. 17, 2023, as Appl. No. 18/380,828.
Prior Publication US 2025/0125001 A1, Apr. 17, 2025
Int. Cl. G11C 7/00 (2006.01); G11C 13/00 (2006.01); G11C 29/00 (2006.01); G11C 29/52 (2006.01)
CPC G11C 29/76 (2013.01) [G11C 13/0064 (2013.01); G11C 29/52 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method of operating a memory circuit, the memory circuit comprising a memory array having a memory portion and a spare portion, the method comprising:
receiving a first write command to a first memory address, wherein the first memory address has a status of being mapped to a first spare memory address, and wherein the first memory address corresponds to a first memory location in the memory portion and the first spare memory address corresponds to a first spare memory location in the spare portion;
performing, in response to the first write command, a first write operation by attempting to write first data to the first memory location;
determining if the first write operation is successful; and
unmapping, in response to the first write operation of being successful, the first memory address from the first spare memory address.