US 12,406,746 B2
Semiconductor storage apparatus capable of efficiently performing screening test
Yasushi Imai, Nagano (JP)
Assigned to ABLIC Inc., Nagano (JP)
Filed by ABLIC Inc., Nagano (JP)
Filed on Aug. 17, 2023, as Appl. No. 18/451,113.
Claims priority of application No. 2022-136614 (JP), filed on Aug. 30, 2022.
Prior Publication US 2024/0071551 A1, Feb. 29, 2024
Int. Cl. G11C 29/50 (2006.01); G11C 29/34 (2006.01); G11C 16/04 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/50 (2013.01) [G11C 29/34 (2013.01); G11C 16/0433 (2013.01); G11C 2029/1204 (2013.01); G11C 2029/5004 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor storage apparatus, comprising:
a wright-voltage switching circuit;
a memory array;
a wright-voltage supply circuit connected to the memory array through the wright-voltage switching circuit;
a bit line discharge circuit; and
a bit line discharge control circuit connected to the memory array through the bit line discharge circuit, wherein the wright-voltage supply circuit supplies at least two types of sense line wright-voltages to the wright-voltage switching circuit,
wherein the wright-voltage switching circuit individually supplies voltages to at least two groups of sense lines in the memory array,
wherein the bit line discharge control circuit outputs at least two types of bit line discharge control signals to the bit line discharge circuit, and
wherein the bit line discharge circuit individually supplies discharge voltages to at least two groups of bit lines in the memory array.