US 12,406,745 B2
Memory repair device
Jun Soo Kwack, Cheongju-si (KR); and Yong Sup Lee, Cheongju-si (KR)
Assigned to MAGNACHIP SEMICONDUCTOR, LTD., Cheongju-si (KR)
Filed by Magnachip Semiconductor, Ltd., Cheongju-si (KR)
Filed on May 10, 2023, as Appl. No. 18/195,418.
Claims priority of application No. 10-2022-0136525 (KR), filed on Oct. 21, 2022.
Prior Publication US 2024/0136007 A1, Apr. 25, 2024
Prior Publication US 2024/0233853 A9, Jul. 11, 2024
Int. Cl. G11C 29/44 (2006.01); G11C 29/00 (2006.01); G11C 29/36 (2006.01)
CPC G11C 29/4401 (2013.01) [G11C 29/36 (2013.01); G11C 29/789 (2013.01); G11C 2029/3602 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory repair device comprising:
at least one memory block including at least one memory;
a memory control unit configured to inspect sizes of the at least one memory and group the at least one memory of a same size into a corresponding memory block; and
a repair information control block configured to:
perform a Built-in Self-Test (BIST) for each memory block of the at least one memory block, and
when a fault cell is detected as a result of the BIST, receive and store repair information related to the fault cell in a repair information storage block,
wherein the memory block is configured to repair the fault cell with a redundancy cell according to the repair information when the memory block loads the repair information during operation of the at least one memory.