| CPC G11C 17/18 (2013.01) [G06F 7/5443 (2013.01); G11C 17/16 (2013.01); G11C 13/0021 (2013.01)] | 16 Claims |
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1. A memory device, for performing an in-memory computation, the memory device comprising:
a plurality of memory cells, forming a plurality of memory strings each performing a sum-of-product computation that is a sum operation for a product computation of each of the memory cells, each of the memory cells stores a weight value, and each of the memory cells comprising:
a transistor, having a gate, a drain and a source, the gate receives an input voltage, the input voltage indicates an input value, when the transistor operates at a first operating point, the input voltage is equal to a first input voltage, when the transistor operates at a second operating point, the input voltage is equal to a second input voltage, the second input voltage is higher than the first input voltage; and
a resistor, connected to the drain and the source of the transistor, when the resistor operates in a first state, the weight value is equal to a first weight value, when the resistor operates in a second state, the weight value is equal to a second weight value,
wherein, each of the memory cells performs the product computation of the input value and the weight value, and each of the memory strings is respectively connected to a load capacitor and generates an output current, and a charging time for the output current to charge the load capacitor reflects a sum-of-product result of the sum-of-product computation.
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