US 12,406,741 B2
Semiconductor memory devices with backside heater structure
Meng-Sheng Chang, Chu-bei (TW); and Yao-Jen Yang, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 7, 2023, as Appl. No. 18/165,635.
Claims priority of provisional application 63/396,699, filed on Aug. 10, 2022.
Prior Publication US 2024/0055062 A1, Feb. 15, 2024
Int. Cl. G11C 17/16 (2006.01); H01L 23/48 (2006.01); H10B 20/25 (2023.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01)
CPC G11C 17/165 (2013.01) [H01L 23/481 (2013.01); H10B 20/25 (2023.02); H10D 30/6735 (2025.01); H10D 62/121 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a memory cell including a transistor and a resistor operatively coupled to each other in series, wherein the transistor and the resistor are formed on a frontside of a substrate; and
a heater structure, disposed on a backside of the substrate opposite to the frontside, that includes a plurality of backside metal wiring levels patterned to form interconnect structures that are electrically isolated from but thermally coupled through the substrate to the resistor, wherein the heater structure is configured to elevate a temperature of the resistor when the memory cell is being programmed.