US 12,406,740 B2
Memory configured to perform a channel precharge operation and method of operating the memory
Hee Youl Lee, Icheon-si Gyeonggi-do (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si Gyeonggi-do (KR)
Filed on Nov. 21, 2023, as Appl. No. 18/515,975.
Claims priority of application No. 10-2023-0101597 (KR), filed on Aug. 3, 2023.
Prior Publication US 2025/0046385 A1, Feb. 6, 2025
Int. Cl. G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3427 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A memory comprising:
a cell string including a first select transistor, a plurality of cell transistors, and a second select transistor; and
a row circuit configured to drive a first select line for controlling the first select transistor, a second select line for controlling the second select transistor and word lines for controlling the cell transistors,
wherein the row circuit differently performs a discharge operation of the first select line according to a position in the cell string of a program target cell transistor from the plurality of cell transistors.