| CPC G11C 16/3427 (2013.01) [G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01)] | 20 Claims |
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1. A semiconductor storage device comprising:
a first word line provided in a first layer extending in a first direction and a second direction that intersects the first direction;
a second word line provided opposite to the first word line in the first layer and controlled independently of the first word line;
a third word line provided in a second layer extending in the first direction and the second direction and stacked on the first layer in a third direction that intersects the first direction and the second direction;
a fourth word line provided opposite to the third word line in the second layer and controlled independently of the third word line;
a fifth word line provided in a third layer extending in the first direction and the second direction and stacked on the second layer in the third direction;
a sixth word line provided opposite to the fifth word line in the third layer and controlled independently of the fifth word line;
a first select gate line disposed in a fourth layer stacked on the third layer in the third direction and extending in the first direction;
a second select gate line disposed opposite to the first select gate line in the fourth layer and controlled independently of the first select gate line;
a third select gate line disposed adjacent to the second select gate line in the fourth layer and controlled independently of the first select gate line and the second select gate line;
a fourth select gate line disposed opposite to the third select gate line in the fourth layer and controlled independently of the first to third select gate lines;
a first memory pillar extending in the third direction and including a first memory cell, a first select transistor electrically connected in series to the first memory cell, a second memory cell, and a second select transistor electrically connected in series to the second memory cell;
a second memory pillar extending in the third direction and including a third memory cell and a third select transistor electrically connected in series to the third memory cell, and a fourth memory cell and a fourth select transistor electrically connected in series to the fourth memory cell;
a third memory pillar extending in the third direction and including a fifth memory cell, a fifth select transistor electrically connected in series to the fifth memory cell, a sixth memory cell, and a sixth select transistor electrically connected in series to the sixth memory cell;
a fourth memory pillar extending in the third direction and including a seventh memory cell and a seventh select transistor electrically connected in series to the seventh memory cell, and an eighth memory cell and an eighth select transistor electrically connected in series to the eighth memory cell; and
a logic control circuit configured to perform a read operation to read threshold voltages of the first to eighth memory cells, respectively, wherein
the first to eighth memory cells are interposed between the first word line and the second word line,
the first, third, fifth, and seventh memory cells are disposed opposite to the first word line,
the second, fourth, sixth, and eighth memory cells are disposed opposite to the second word line,
the first and second select transistors are interposed between the first and second select gate lines,
the third and fourth select transistors are interposed between the second and third select gate lines,
the fifth and sixth select transistors are interposed between the third and fourth select gate lines,
the seventh and eighth select transistors are interposed between the first and fourth select gate lines,
the first and seventh select transistors are electrically connected to the first select gate line,
the second and fourth select transistors are electrically connected to the second select gate line,
the third and fifth select transistors are electrically connected to the third select gate line,
the sixth to eighth select transistors are electrically connected to the fourth select gate line, and
when performing the read operation on one of the first to eighth memory cells, the logic control circuit independently controls each of the first to fourth select gate lines such that the select transistors electrically connected to the first to eighth memory cells other than the memory cell to be read are turned off.
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