US 12,406,738 B2
Determining offsets for memory read operations
Jie Zhou, Shanghai (CN); Xiangang Luo, Fremont, CA (US); Min Rui Ma, Shanghai (CN); and Guang Hu, Mountain View, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 4, 2024, as Appl. No. 18/733,187.
Application 18/733,187 is a continuation of application No. 17/637,766, granted, now 12,027,213, previously published as PCT/CN2021/081761, filed on Mar. 19, 2021.
Prior Publication US 2024/0404604 A1, Dec. 5, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/00 (2006.01); G11C 16/26 (2006.01); G11C 29/02 (2006.01); G11C 29/52 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 29/028 (2013.01); G11C 29/52 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory arrays; and
processing circuitry coupled with the one or more memory arrays and configured to cause the memory system to:
perform a first plurality of read operations on a block of the one or more memory arrays using a reference voltage and an offset value;
determine that a quantity of successful read operations of the first plurality of read operations exceeds a threshold quantity, wherein the quantity of successful read operations comprises read operations that are successfully performed using the reference voltage and the offset value; and
perform, in accordance with the quantity of successful read operations exceeding the threshold quantity, a second plurality of read operations on the block of the one or more memory arrays using the reference voltage and a fixed offset value that is in accordance with the offset value.