| CPC G11C 16/24 (2013.01) [G11C 5/063 (2013.01); G11C 16/08 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02)] | 20 Claims |
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1. A 3D memory, including:
a plurality of tiles, disposed on a substrate, wherein one of the plurality of tiles includes a first sub-tile located in a first region of the substrate and a second sub-tile located in a second region of the substrate;
a bit line transistor structure, disposed on the substrate and is located between the first sub-tile and the second sub-tile, including a first bit line transistor structure located in the first region and a second bit line transistor structure located in the second region;
a first upper conductive layer, disposed on the substrate, including:
a plurality of local bit line, extending along a first direction and including a first group of local bit lines and a second group of local bit lines, wherein the first group of local bit lines and the second group of local bit lines are separated from each other in the first direction;
a plurality of local source lines, extending along the first direction, wherein two adjacent local bit lines among the plurality of local bit lines are disposed between adjacent two local source lines; and
a conductive pattern, disposed between the first group of local bit lines and the second group of local bit lines in the first direction, and is disposed between the adjacent two local source lines in a second direction; and
a second upper conductive layer, disposed on the first upper conductive layer, including:
a global bit line, electrically connected to the first group of local bit lines and the second group of local bit lines through the conductive pattern.
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