US 12,406,734 B2
One time programmable memory cell
Ying Yan, Shanghai (CN)
Assigned to Shanghai Huali Microelectronics Corporation, Shanghai (CN)
Filed by Shanghai Huali Microelectronics Corporation, Shanghai (CN)
Filed on Sep. 15, 2023, as Appl. No. 18/368,691.
Claims priority of application No. 202311085047.8 (CN), filed on Aug. 25, 2023.
Prior Publication US 2025/0069666 A1, Feb. 27, 2025
Int. Cl. G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/0433 (2013.01); G11C 16/26 (2013.01); G11C 2216/26 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A one time programmable memory cell, comprising an anti-fuse programmable transistor, a fuse, and two control transistors;
a gate end of the anti-fuse programmable transistor being used as a Q end of the one time programmable memory cell, the Q end being configured to be connected to a bit line;
one of a source end and a drain end of a first control transistor being connected to one of a source end and a drain end of the anti-fuse programmable transistor, the other of the source end and the drain end of the first control transistor being connected to one of a source end and a drain end of a second control transistor and one end of the fuse, a gate end of the first control transistor being used as a WL end of the one time programmable memory cell, the WL end being configured to be connected to a main word line;
the other of the source end and the drain end of the second control transistor being connected to a ground, a gate end of the second control transistor being used as a WL_P end of the one time programmable memory cell, the WL_P end being configured to be connected to an auxiliary word line; and
the other end of the fuse being used as an FS end of the one time programmable memory cell, the FS end being configured to be connected to a state select line.