| CPC G11C 16/102 (2013.01) [G11C 16/0433 (2013.01); H03K 19/01721 (2013.01)] | 4 Claims |
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1. A configuration control circuit of a flash-type field programmable gate array (FPGA) capable of suppressing a programming interference, wherein the configuration control circuit comprises a word line (WL) circuit, a bit line (BL) circuit, and a programming selection circuit;
the WL circuit comprises a plurality of WL channels, and each of the plurality of WL channels corresponds to one row of a memory array, and is configured to provide a WL voltage to each flash memory cell in the corresponding row;
the BL circuit comprises a plurality of BL channels, and each of the plurality of BL channels corresponds to one column of the memory array, and is configured to provide a BL voltage to each flash memory cell in the corresponding column by using the programming selection circuit; and
when a programming operation is performed on a flash memory cell located in a target row and a target column, a programming WL voltage is provided through a WL channel corresponding to the target row, and a programming BL voltage is provided through a BL channel corresponding to the target column; and the programming selection circuit controls a path between the programming BL voltage and a BL voltage obtaining terminal of the flash memory cell located in the target row and the target column to be turned on, and a path between the programming BL voltage and a BL voltage obtaining terminal of a flash memory cell located in another row and the target column to be turned off;
wherein the programming selection circuit comprises a plurality of selection channels and a plurality of selection transistors, each of the plurality of selection transistors corresponds to one flash memory cell, a drain of each of the plurality of selection transistors is connected to the BL voltage obtaining terminal of the corresponding flash memory cell, and sources of selection transistors connected to all flash memory cells in a same column are connected to each other and connected to a BL channel corresponding to the column; and each of the plurality of selection channels corresponds to one row of the memory array, and gates of selection transistors connected to all flash memory cells in a same row are connected to each other and connected to a selection channel corresponding to the row; and
the programming selection circuit outputs a valid-level selection voltage through a selection channel corresponding to the target row, and outputs an invalid-level selection voltage through a selection channel corresponding to the another row;
wherein each of the plurality of selection channels comprises a first programming switch transistor, a pull-up selection switch transistor, a second programming switch transistor, and a pull-down selection switch transistor, wherein a supply voltage VDD, the pull-up selection switch transistor, the first programming switch transistor, the second programming switch transistor, the pull-down selection switch transistor, and a negative high voltage LV1 are sequentially connected, and a common terminal of the first programming switch transistor and the second programming switch transistor is led out to connect the gates of the selection transistors connected to the flash memory cells in the corresponding row;
the second programming switch transistor is controlled by a programming operation signal, the first programming switch transistor is controlled by a complementary signal of the programming operation signal, and the pull-up selection switch transistor and the pull-down selection switch transistor are controlled by a gating trigger signal;
when the programming operation is performed on the flash-type FPGA, the programming operation signal has a valid level, second programming switch transistors of all the plurality of selection channels are turned on, and first programming switch transistors of all the plurality of selection channels are turned on;
a gating trigger signal in the selection channel corresponding to the target row has the valid level, the pull-down selection switch transistor in the current selection channel is turned on, the pull-up selection switch transistor in the current selection channel is turned off, and the current selection channel outputs the negative high voltage LV1 to a gate of a selection transistor connected to the flash memory cell in the target row to control the selection transistor to be turned on; and
a gating trigger signal in the selection channel corresponding to the another row has an invalid level, the pull-up selection switch transistor in the selection channel corresponding to the another row is turned on, the pull-down selection switch transistor in the selection channel corresponding to the another row is turned off, and other selection channels each output the supply voltage VDD to a gate of a selection transistor connected to a flash memory cell in each row to control the selection transistor to be turned off.
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