US 12,406,732 B2
Method of programming flash memory
Devin Verreck, Pellenberg (BE); and Maarten Rosmeulen, Ghent (BE)
Assigned to IMEC vzw, Leuven (BE)
Filed by IMEC VZW, Leuven (BE)
Filed on Sep. 28, 2023, as Appl. No. 18/477,456.
Claims priority of application No. 22198979 (EP), filed on Sep. 30, 2022.
Prior Publication US 2024/0112737 A1, Apr. 4, 2024
Int. Cl. G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/16 (2013.01); G11C 2216/02 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method for operating a NAND flash memory, comprising:
providing the NAND flash memory, the NAND flash memory comprising:
a semiconductor channel layer,
a first gate arranged on a first side of the channel layer and extending along the channel layer, and
a plurality of second gates arranged on a second side of the channel layer and sequentially along the channel layer, wherein each second gate is associated with a memory cell of the NAND flash memory and connected to one of a plurality of word lines;
applying a first voltage to the first gate and a pass voltage to one or more word lines to inject charge into the channel layer positioned next to one or more second gates and form one or more charge packets from the charge in the channel layer, wherein each charge packet is formed adjacent to one of the one or more second gates; and
applying a programming voltage to the one or more word lines to move the one or more charge packets from the channel layer into one or more charge storage layers associated with the one or more second gates adjacent to which the one or more charge packets are formed.