US 12,406,731 B2
Dynamic latches above a three-dimensional non-volatile memory array
Jiewei Chen, Meridian, ID (US); Mithun Kumar Ramasahayam, Meridian, ID (US); Tomoko Ogura Iwasaki, San Jose, CA (US); June Lee, Sunnyvale, CA (US); and Luyen Vu, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 24, 2023, as Appl. No. 18/237,815.
Claims priority of provisional application 63/401,052, filed on Aug. 25, 2022.
Prior Publication US 2024/0071505 A1, Feb. 29, 2024
Int. Cl. G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/3459 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
storing a multi-bit data pattern in a plurality of latches in a logic layer disposed above the memory array, the multi-bit data pattern representing a sequence of bits to be programmed to respective memory cells of a plurality of sub-blocks of a block of the memory array;
pre-charging the plurality of sub-blocks according to the multi-bit data pattern; and
causing a single programming pulse to be applied to a selected wordline of a plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.