| CPC G11C 16/08 (2013.01) [G11C 5/063 (2013.01); G11C 16/0483 (2013.01); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] | 19 Claims |
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1. A memory device comprising:
a first semiconductor structure including a peripheral circuit which is defined in a cell region of a substrate, a plurality of pass transistors which are defined in a row decoder region of the substrate, a first bonding layer which includes a plurality of first bonding pads, and a plurality of bottom wiring layers which are disposed between the substrate and the first bonding layer;
a second semiconductor structure disposed on the first semiconductor structure, and including a second bonding layer which includes a plurality of second bonding pads bonded to the plurality of first bonding pads, a memory cell array, and at least one top wiring layer which is disposed between the second bonding layer and the memory cell array; and
a plurality of global lines disposed in the row decoder region, and configured to transfer operating voltages to the plurality of pass transistors,
wherein the plurality of bottom wiring layers include bottom wiring layers of a first tier and bottom wiring layers of a second tier which are disposed over the bottom wiring layers of the first tier, and
wherein the plurality of global lines are disposed in at least one of the bottom wiring layers of the first tier.
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