US 12,406,729 B2
Non-volatile memory with inter-die connection
Shiqian Shao, Fremont, CA (US); Tuan Pham, San Jose, CA (US); and Fumiaki Toyama, Cupertino, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Sandisk Technologies, Inc., Milpitas, CA (US)
Filed on May 26, 2022, as Appl. No. 17/825,337.
Prior Publication US 2023/0386576 A1, Nov. 30, 2023
Int. Cl. G11C 5/04 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC G11C 16/0483 (2013.01) [G11C 16/14 (2013.01); G11C 16/26 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A non-volatile memory apparatus, comprising:
a first integrated memory assembly comprising a first memory die directly connected to a first control die, the first memory die comprises a first non-volatile memory structure and a first top metal layer above the first non-volatile memory structure, the first control die comprises a first substrate and a first control circuit positioned on the substrate, the first control die further comprises a first set of metals layers above the first control circuit, the first control circuit is configured to perform memory operations on the first non-volatile memory structure; and
a second integrated memory assembly comprising a second memory die directly connected to a second control die, the second memory die comprises a second non-volatile memory structure and a second top metal layer above the second non-volatile memory structure, the second control die comprises a second substrate and a second control circuit positioned on the substrate, the second control die further comprises a second set of metals layers above the second control circuit, the second control circuit is configured to perform memory operations on the second non-volatile memory structure, the second integrated memory assembly is stacked on top of the first integrated memory assembly, the second substrate comprises a set of conductive vias extending completely through the second substrate that connect at one end to the first top metal layer of the first memory die of the first integrated memory assembly.