| CPC G11C 16/0483 (2013.01) [H01L 21/76843 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] | 28 Claims |

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1. A microelectronic device, comprising:
a stack structure comprising blocks each including a vertically alternating sequence of conductive material and insulative material arranged in tiers, at least one of the blocks comprising:
a memory array region having vertically extending strings of memory cells within a horizontal area thereof; and
a staircase region horizontally neighboring the memory array region and comprising:
a staircase structure having steps comprising horizontal ends of the tiers; and
a crest sub-region horizontally interposed between the staircase structure and the memory array region, an uppermost boundary of the tiers within the crest sub-region vertically underlying an uppermost boundary of the tiers within the memory array region;
filled slot structures interposed between the blocks of the stack structure; and
dielectric material substantially continuously horizontally extending over and between the blocks of the stack structure, a vertical thickness of a portion of the dielectric material overlying the crest sub-region of the staircase region of the at least one of the blocks greater than a vertical thickness of an additional portion of the dielectric material overlying the memory array region of the at least one of the blocks.
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